How did RISC-V grab the attention of nearly every major tech company and what was the need for yet another computer processor architecture? Tom walks you through the history and use case of RISC-V.
Featuring Tom Merritt.
Please SUBSCRIBE HERE.
A special thanks to all our supporters–without you, none of this would be possible. Become a supporter at the Know A Little More Patreon page for exclusive content and ad-free episodes.
Thanks to Kevin MacLeod of Incompetech.com for the theme music.
Thanks to Garrett Weinzierl for the logo!
Thanks to our mods, Kylde, Jack_Shid, KAPT_Kipper, and scottierowland on the subreddit
Send us email to feedback@dailytechnewsshow.com
Episode transcript:
We have an episode of Know a Little More about ARM. It’s the plucky alternative to Intel and AMD. Rough and raw and faster. That’s because Intel and AMD make chips based on the x86 Instruction Set Architecture or ISA. x86 is what is known as a Complete Instruction Set Computer or CISC. Arm is faster and more power efficient because it’s a Reduced Instruction Set Computer or RISC.
But there’s always a smaller more agile and younger fish about to eat your lunch. And for ARM that smaller younger fish is called RISC V.
Let’s help you Know a little more about RISC-V.
First let’s back up and get a little background on RISC itself.
As I mentioned, RISC stands for Reduced Instruction Set Computing
To properly explain RISC we’d have to explain how chips work entirely and that could end up making this an 8 hour episode.
So let’s make all the engineers cringe and skip a bunch of steps with the hopes that you’ll have a general understanding even if it’s not precise.
If you promise not to make too many inferences from these oversimplifications, I’ll promise to buy the chip engineers a drink anytime they see me at a bar or juice shop to make up for it. Just tell me “I know a LOT more about RISC” and I’ll know.
OK so with that in mind, let’s define the couple of things we need to know. A processor register, or usually just referred to as a register, is a place where the CPU can quickly store some data and perform a quick operation on it and then send the resulting data back to main memory. Registers are paired up with the instruction set aka the set of opcodes.
So registers. They are essential for processing the instructions
NEXT. A compiler is a program that translates code from one computer language to another. So like taking something written in C++ and making it machine code.
So the compiler translates the code.
Got it? Register and compiler.
OK now back to the story of RISC.
In 1975 the fastest mainframe was the IBM 370/168. It could process 3.5 million instructions per second.
John Cocke and team at IBM were trying to build a digital telephone switch that could handle 1 million calls per hour. And to do that the CPU would have to handle 12 million instructions per second. Just less than 4 times the speed of the fastest mainframe.
Moore’s law was Moore’s law so they were only going to get faster hardware at Moore’s law pace. But maybe there was something they could do in the software of the chip to speed things up.
Cocke’s team took advantage of two things IBM had learned from its customers.
One is that high-performance computers often ran out of processor registers. As you might have guessed, they figured adding more registers could improve performance.
Two, compilers generally ignored the majority of available instructions instead just picking the fastest versions.
That second was the key.
Cocke’s team removed instructions, which meant you had more available registers, which had the same effect as if you added registers, which sped up the CPU.
Success right? Well sort of. The telephone program was canceled in 1975 but it turned out the reduced instruction approach sped up almost any code, not just telephone switches.
The theory was implemented as the IBM 801 which was produced as the IBM ROMP in 1981. It was used mostly in peripherals though it showed up in the CPU of the IBM RT PC in 1986. Which was a flop.
But that’s kind of proto-RISC. There were two chip architectures considered the direct birth of RISC. And they didn’t come from IBM. They came from silicon valley’s top schools, Berkley and Stanford.
In 1978, computer scientist Andrew S. Tanenbaum demonstrated that a 10,000 line program could be represented by a simplified instruction set architecture, coming to similar conclusions as the IBM team.
So between IBM’s work and Tanenbaum’s findings the ground was laid for MIPS and Berkeley-RISC, which would both go on to be successfully commercialized.
David Patterson’s Cal-Berkeley RISC project reduced the instructions, and added some circuitry to assist the compiler. It also used something called Register windows, which limited how many registers a program could use at once to make it faster.
At Stanford, John L. Hennessy led a team that developed MIPS for Microprocessor without Interlocked Pipeline Stages. It reduced instructions and actually added registers. This work was commercialized by the MIPS computer systems company founded in 1984 and now called MIPS Technologies Inc.
This time the idea caught on. The MIPS R2000 went on sale in January 1986, followed by the HP PA-RISC and the Sun Microsystems SPARC processor based on the Berkeley RISC-II system and of course eventually the PowerPC which Apple used for years.
One of the most successful RISC ventures was ARM which built its business on selling a license to its instruction set without having to make the chips itself. ARM makes its money by licensing as does MIPS.
Now whenever you have a company making money licensing software, you have a group trying to make an open source alternative. For every Windows there is a Linux.
Along the way several efforts were made to offer open source instruction sets that you would not need to pay a royalty to use. ARM’s first two versions in fact, had a public-domain instruction set still supported by the GNU Compiler Collection, aka GCC. OpenRISC has GCC and Linux support but not many commercial implementations.
So it was not seen as particularly unusual that Cal-Berkeley’s Krste Asanović decided to spend the summer of 2010 satisfying his research requirement for an open-source computer system. He was lucky enough to get David Patterson, the Berkeley-RISC innovator himself to help with the project. Since Patterson considered it the fifth time he had helped make a RISC architecture they called the project RISC-V, even though RISC-V bears no direct relationship to the previous 4 attempts.
They sourced the documents and designs under the BSD Licenses. But there was enough interest in RISC-V that in 2011 they published the Instruction Set Architecture, and later placed it under a Creative Commons license. The upshot is that unlike some open source licenses, this one lets companies change the code and they don’t have to contribute their changes back to the main project. They can make their versions proprietary derivative works. It’s because of this possibility that the RISC foundation considers RISC-V a royalty-free open standard not open source.
What is the RISC Foundation? Glad you asked.
Lots of companies were interested in RISC-V but worried about its stability. Would they build on RISC-V and then people lose interest in maintaining it? Maybe ARM was safer.
So in 2015 the authors and owners of RISC-V assigned their rights to the RISC-V foundation. In November 2019 it moved to Switzerland to avoid any controversy over US trade regulations. And in March 2020 was reorganized as a Swiss nonprofit business association called RISC-V International.
Anyone can freely use RISC-V designs and know that an organization exists to keep the project stable. Only members of RISC-V International can approve changes to the standard and only member organizations can use the trademarked compatibility logo.
There are more than 3,000 members including Intel, Qualcomm, AMD Xilinx, Arduino, Nvidia, NXP, Huawei, Meta, Google, Alibaba, Seagate, Tencent, Samsung, Siemens, Sony, … actually it’s probably faster to note that Apple and Microsoft are not members.
In its first ten years RISC-V has been used mostly in embedded applications and microcontrollers, but that is beginning to change.
The first RISC-V laptop, the Roma shipped from Alibaba in October 2022.
And in August 2023, RISC Foundation members Qualcomm, NXP, Nordic Semiconductor, Infineon and Robert Bosch set up a company in Germany to commercialize RISC-V-based products.
They’ll start with cars and Internet-of-things but don’t intend to limit themselves to those.
While most companies who want a RISC architecture will continue to rely on ARM, those who want the freedom to change the architecture, which ARM’s licenses generally don’t allow, may try RISC-V. And whether it’s the Qualcomm-driven company or someone else, there’s an appetite for a more affordable RISC-V based product to give companies an alternative to ARM when wanting the faster low-power RISC chips vs. the traditional x86 style chips.
In other words, I hope you know a little more about RISC-V.
CREDITS
Know A Little More is researched, written and hosted by me, Tom Merritt. Editing and production provided by Anthony Lemos and Dog and Pony Show Audio. It’s issued under a Creative Commons Share Attribution 4.0 International License.